Forum Discussion
999timur999
New Contributor
New Contributor# ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 90 ns.
my project suddenly gave an error [[ # ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 90 ns. ]] after i added the values on the first input (B)
But when at input B=0 ...
Nurina
Regular Contributor
Regular ContributorNot waveform to verilog, the error comes from converting bdf to verilog. This is what the simulator does. It converts your bdf design into code for it to create a testbench and then only performs simulation. Sometimes this conversion does not work the way you want them to.
Regards,
Nurina
999timur999New Contributor
New ContributorOK, thanks, can I refer to your answer as a specialist's answer in my diploma?
