# ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 90 ns.

Not waveform to verilog, the error comes from converting bdf to verilog. This is what the simulator does. It converts your bdf design into code for it to create a testbench and then only performs simulation. Sometimes this conversion does not work the way you want them to.

Regards,

Nurina