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Altera_Forum
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13 years ago

Why Vectored Interrupt Controller IRQ -1 ?

Hello Friends i have added Vectored Interrupt Controller and generate the BSP but system.h reflect that VIC IRQ is -1 /* VIC configuration */ #define ALT_MODULE_CLASS_VIC altera_vic #def...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You set TEMP_OUT to 1 then you immediately deassert it to 0. If you are sure your isr is being serviced, then you simply can't see the pulse on oscilloscope because the signal doesn't have enough time to switch high.

Add some delay before IOWR_ALTERA_AVALON_PIO_DATA(TEMP_OUT_BASE,0x0)

You could also toggle TEMP_OUT upon receipt of edge_capture and then connect the pio to some logic which generates a fixed length pulse on each transition.