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Altera_Forum
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11 years ago

Why qsys doesn't report error when Avalon-MM data width mismatch?

I have a design which I want to connect a DDR3 controller (DDR3 SDRAM Controller with UniPHY) to an Avalon-MM Pipeline Bridge, then the bridge connects with the nios II. (Nios <-----> Bridge <-----> ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

One can suspect that, behind the scenes, QSYS will connect the lower order address bits of the 32 bit wide interface to the byte enable signals on the 256 bit interface. However, it might be a good idea to look at the generated files and verify what is actually occurring.