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Altera_Forum
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11 years ago

Why qsys doesn't report error when Avalon-MM data width mismatch?

I have a design which I want to connect a DDR3 controller (DDR3 SDRAM Controller with UniPHY) to an Avalon-MM Pipeline Bridge, then the bridge connects with the nios II. (Nios <-----> Bridge <-----> ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

Read this document to gain a better understanding of what you are telling Qsys to do:

http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf

Adapting mismatched widths is a feature.

--- Quote End ---

Thanks. I did skim the file quickly but I didn't notice it. I will read it carefully again.