Why PIO does not follow addressing rules ?

The PIO actually has a 32-bit avalon interface regardless of how many bits you specify the PIO to be. The simplest thing for you to do is to make your custom peripheral have a 32 bit data bus, even if you're not using all of it.

Here the code of the vhd file generated by the SOPC Builder for a PIO component of 8 bits. It appears that the data bus width is 8 and not 32.

library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led_pio is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal chipselect : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal write_n : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
              -- outputs:
                 signal out_port : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
              );
end entity led_pio;
architecture europa of led_pio is
                signal clk_en :  STD_LOGIC;
                signal data_out :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal read_mux_out :  STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
  clk_en <= std_logic'('1');
  --s1, which is an e_avalon_slave
  read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 8) AND data_out;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic_vector'("00000000");
    elsif clk'event and clk = '1' then
      if std_logic'(((chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then 
        data_out <= writedata(7 DOWNTO 0);
      end if;
    end if;
  end process;
  readdata <= read_mux_out;
  out_port <= data_out;
end europa;

What you'd really want to look at is the ".sopcinfo" file. For the PIO you will find a subsection like this:

 <parameter name="addressAlignment">
    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
    <value>NATIVE</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid></parameter>

Ok thanks for the explanation. But I find that it is quite strange that a "default" component provided by Altera does not follow the recommendations.

It's pretty common now actually. SoPC builder has been evolving rapidly the last few years. The PIO is an old component. I'm sure it would be quite time consuming to do a complete rewrite of every component supported by SoPC builder every time it evolved (yet that's what I do with all my components). That's why they deprecated "NATIVE" addressing rather than obsoleting it.