Honored Contributor
Honored Contributorthanks :). I tried that flag and it enables the interrupt to be received.
But now I have another problem....I only get 1 of the descriptors being processed. After an interrupt when I check the descriptors to see the result, only the 1st one shows an ActualBytesTransferred with something in it (i.e. 0xFFFF)....the others stay at 0, and also have no errors or anything in their control flags. In my SOPC, the SGDMA is set to enable burst transfers, read burst width 8, Data Width 8, memory to memory, enable bursting on descriptor read master set to = off. I have 32MB of DDR2 memory at avalon base 0x8000000. I logically divide it into 4 x 8MB regions. I use the 1st 16KB of the region to keep hold of the set of SGDMA descriptors, and after that is the actual data that I want to transfer out into PC Host memory. I am setting up a chain of descriptors which each have a bytes to transfer of 0xFFFF (have also tried 0xF000 in case of alignment issues? i.e. needs to be 32bit aligned for instance). I have the hardwareowner flag set on those 10 descriptos to = 1, and I have a final descriptor with an owner flag of = 0, so 11 descriptors in total. The first descriptor points to the next descriptor using avalon base addresses e.g. first descriptor is at 0x8000000, next one is at 0x8000020, etc...and I put the 0x8000020in the next descriptor field of the 1st descriptor, etc. The destination address is a PCIe address which has been correctly masked off. I see the actual data that was in the Avalon DDR buffer received in the Host memory correctly....all 0xFFFF bytes of it. I put the descriptors in avalon memory using WRITE_REGISTER_BUFFER_UCHAR calls. The size of my descriptor struct is 32bytes (and is packed properly). When I receive the interrupt and check the status flag it says ChainCompleted. So I am stuck on how to get it to actually do work with the other descriptors!
