why o why don't I get an interrupt when SGDMA engine completes a descriptor or chain

They are components that show up in the component listing once they are part of the IP search path. There is an /ip directory in that file, if you copy that directory to your hardware project then the cores will appear in SOPC Builder the next time you open the tool.

They can target any Altera FPGA. For what you are doing you would want memory to memory transfers so you would configure the cores similar to what is used in the design example. Conceptually this mSGDMA is similar to the non-SGDMA you started your project with except it buffers multiple descriptors internally.

It doesn't support descriptor pre-fetching so in order to get that functionality you would need some sort of intelligent block to sit in front of the dispatcher (buffer) block to handle descriptor fetching. There are many ways to implement this, for example I would use a Nios II 'e' core to perform descriptor fetching, or a state machine, or a microcode sequencer, etc...