Why my system cannot boot from EPCS

RemyMartin,

you also have to make important settings in NIOS II IDE -> System Library Properties. Did you choose the appropriate memories in the linker sections: .text .rodata .rwdata to where your software should run and fetch data?

Mike

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In the SOPC Builder, the reset address is pointed to the base address of EPCS.[/b]

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I think u can&#39;t point to the base address of EPCS, because in that address will reside the configuration data of FPGA. Try to set the reset address in the EPCS memory space beyond configuration data.

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originally posted by mir@Jun 13 2005, 03:05 AM

remymartin,

you also have to make important settings in nios ii ide -> system library properties. did you choose the appropriate memories in the linker sections: .text .rodata .rwdata to where your software should run and fetch data?

mike

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Would you want the .text to point to epcs_controller (the EPCS device) while the .rodata and .rwdata point to ext_ram (SDRAM)?

-Jon

jonb: The linker settings should reflect your run-time memory (.text included) -- this probably means SDRAM. Place the Nios II reset address (In SOPC Builder) pointing to the EPCS controller; this is all taht is necessary. After building the project in the IDE, use the flash programmer to program the software; this will program everything into EPCS, and it will then be subsequently copied out of EPCS during boot-up.

..what happens is the .elf (with address:data records for everything in your software) is written into EPCS flash. The EPCS boot-loader copies these out to the desired memory location at boot-time.

Remy: Some notes about EPCS:

- Make sure you&#39;re using Nios II 5.0. There was an EPCS boot-bug (and patch) available for 1.1 but this was fixed in 5.0

- Nios II software boot from EPCS is not currently (directly) supported in Stratix II; Cyclone & Cyclone II are supported.

Thank u all.

I am using the NiosII1.1 and QuartusII4.2

At first, i doubted the reset address conflicted with the hardware image location (just like Soin said); but even after i changed the reset address to another address of epcs which would not conflict the hardware image, the system did not boot sucessfully also.

At last, the FAE told me that there is a bug in system-boot-up-from-epcs, then I fixed it. Now, it works.

By the way, the reset address is also pointed to the base address of epcs. The UG of flash programmer says that "the flash programmer first checks the size of the FPGA configuration data, then appends the software content to the end of it in the epcs device", so we need not worry the reset address will conflict with the hardware image.

Yes, excuse me I was a bit confusing. Infact the reset address in EPCS is not a problem, because the EPCS controller has an onchip-ram in which can be stored a boot code to copy the program code from EPCS to the memory specified in IDE library setting (and the addresses refer to this onchip ram).

sorry again http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif