Honored ContributorHi all,
I'm new to the Nios/Qsys/Eclipse. I've used Quartus software before but never with Nios. I'm using a Nios Gen2 with a MAX10 (BeMicroMAX10). The free version of Nios. The base address of the PIO is for the data. Then there is outset and outclear. That's 3 locations. So how come Qsys shows an address span of 16? Thanks
Honored ContributorHave a look at the documentation for the pio core (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf), chapter 11. Depending on the options, a PIO core uses 4 or 6 32-bit registers. In addition to the pin accesses and direction control, you have a edge capture register and an interrupt mask register.
Honored ContributorYes. Table 11-2 shows offset 0 thru 5. That's 6 addresses? Why the other 9? Thanks
Honored ContributorIn one case there are 6 x 32bit registers. So that means in powers of two there are 8 x 32bit = 32 bytes.
But if you have don't have the extended registers enabled, then there are 3 x 32bit registers - as powers of two that is 4 x 32bit = 16 bytes. Address spans are shown in bytes (even if you are using Word Addressing).Honored ContributorI think the minimum width is 16 bytes.
You should also make your slave 32bits wide - return 0 to reads for the top 24 bits. The Nios acceses are 32bit (with appropriate byte enables for writes) and logic gets added to generate 4 cycles to an 8bit slave.Honored ContributorHonored ContributorYou can make the PIO any width you like. The Avalon-MM slave interface of the PIO core will always be 32bit wide and unused bits will read as 0.
