Why do two Avalon_MM_Pipeline Bridges respond differently to READ

Thank you guys ! The issue was that 1) as was stated by Daixiwen the second bus uses peripherals with two clocks 2) the second bus had Avalon MM FIFOs which have a backpressure feature (waitrequest) which prevents over-run or under-run. This caused the lockup e.g. reading from an empty FIFO. So, the SW has to make sure that there is something in the FIFO before attempting to read it ( similarly, for outgoing the other way make sure the FIFO is not full, etc.)