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Altera_Forum
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13 years ago

Why do two Avalon_MM_Pipeline Bridges respond differently to READ

Hi All, In my design I have two Avalon_MM_Pipeline Bridges connecting to two segments of Avalon busses. In simulation, I can write and read from one perfectly but the second bridge, althoug...
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Altera_Forum
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13 years ago

Are you using different clocks on both sides of the bridge? If yes, QSys/SOPC Builder will add some clock crossing logic that can cause some latency on read transfers.