Why can't I add SDRAM to NiosII1.1+QuartusII4.2

I do a very simple test: building a system( niosII+flash+sram+dma+sdram), the sopc builder can generate the system without errors. But when I synthesis this system, the QuartusII 4.2 give me the following error messages(64 error messages in all, all the messages say the same thing):

.......

Error: Can't process assignment. Attribute format is illegal -- parsing error (line 20). Use legal format for ALTERA_ATTRIBUTE assignment.

.......

When I double click this error message to go into the error source, it is in the "sdram_0.v", but the the "error line " is just a simple Verilog statement, I cannot see any erron in it.

The sdram_0.v is generate by the sopc builder comes with QuartusII4.2, why QuartusII 4.2 say something is wrong with it ?

In additon to the test, the example design comes with nios2 1.1 cannot pass the synthesis also. The error messages also point to the sdram.

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The software upgrade speed of altera is very fast, but the reliability does keep up with it.

We need reliability !