who can help me about double accessed ram?

i have a similar problem ,i want generate a double accessed on chip ram in FPGA,with one side communicating with niosII cpu and the other side communicating with dsp out of FPGA,but i dont know how to make it. you know,each side of the double accessed ram is slave port,when i generate it in sopc buider,the two sides all connect with niosII cpu, how can i made one of the two side of the ram connects with dsp?