What's wrong with my SRAM component of NIOS II?

Hi all,

I am a beginner of NIOS II, and I use Quartus 10.0. My FPGA is EP1C12F256.

Recently, I customized a SRAM component for the SRAM chip K6X4016T3F(256Kx16). I attach the vhdl file below, just realizing a tri-status

gate for the data bus and connecting the other avalon_MM_slave signals to the relative ports. I imported this file, set the system clk of

NIOS as 30MHz(33.3ns), and the timing of this core is(cycles):

setup: 1

read wait: 2

write wait: 2

hold: 1

I also selected the Memory device option in Deprecated list. I used this component and set it as the exception address of the cpu. During

generating this NIOS core, I don't find any information in the report, which is associated with this component. However, I can see information about other component I used, such as "running generator program for epcs_flash_controller".

After I finished this project in Quartus, I set a c application in NIOS II IDE. The .c file is:# include "stdio.h"# include "system.h"# include "altera_avalon_pio_regs.h"

int main(void)

{

printf("hello");

while(1)

{

IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,1);

}

}

I download the .sof to the FPGA first and then I want to run this application.

1. When I click "run as->Nios II hard ware", IDE rebuild this project and download the .elf file to the FPGA. Then nothing comes out and the test IO pin is still 0.

2. When I click "run as->Nios II Instruction set simulator", the error "Unable to load memory block at address 0x200020 from ELF file" comes out.

It seems that the SRAM is not working. But I am sure the pins are correctly connected. My questions are:

1. If a customized component is used in sopc, should I see some information about it in the nios core generating report?

2. Can I simulate the customized memory component in Nios II Instruction set simulator?

3. Can anybody tell me how to solve this problem?