library ieee;
use ieee.std_logic_1164.all;

entity Mtv_IG_Sram is 
	port(	
	
			CSISRAM_clk : in std_logic ;
			CSISRAM_reset_n : in std_logic ;
			
			-- avalon-MM slave interface
			AVSRAM_chipselect_n : in std_logic ;
			AVSRAM_address : in std_logic_vector(19 downto 0) ;
			AVSRAM_byteenable_n : in std_logic_vector(1 downto 0) ;
			AVSRAM_write_n : in std_logic ;
			AVSRAM_writedata : in std_logic_vector(15 downto 0) ;
			AVSRAM_read_n : in std_logic ;
			AVSRAM_readdata : out std_logic_vector(15 downto 0) ;
			
			-- conduit to periphyral
			IGSRAM_Data : inout std_logic_vector(15 downto 0) ;
			IGSRAM_Addr : out std_logic_vector(19 downto 0) ;
			IGSRAM_OE_n : out std_logic ;
			IGSRAM_WE_n : out std_logic ;
			IGSRAM_CS_n : out std_logic ;
			IGSRAM_LB_n : out std_logic ;
			IGSRAM_UB_n : out std_logic 
	);
end Mtv_IG_Sram;

architecture Behavior of Mtv_IG_Sram is 
begin

	IGSRAM_OE_n <= AVSRAM_read_n;
	IGSRAM_WE_n <= AVSRAM_write_n;
	IGSRAM_CS_n <= AVSRAM_chipselect_n;
	IGSRAM_LB_n <= AVSRAM_byteenable_n(0);
	IGSRAM_UB_n <= AVSRAM_byteenable_n(1);
	IGSRAM_Data <= AVSRAM_writedata when AVSRAM_write_n = '0' else (others=>'Z') ;
	IGSRAM_Addr <= AVSRAM_address ;				
	AVSRAM_readdata <= IGSRAM_Data ;	
		
end Behavior;