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Altera_Forum
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11 years ago

What's the difference between an Avalon MM Master and an Avalon MM Slave

I need to design an Avalon MM IP component that allows software running on the HPS of a Cyclone V FPGA to access an external comms chip and an SRAM chip. The comms chip has a memory mapped register s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks for that Ted, it's very useful. I'll start designing my Avalon MM Slave component.