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Altera_Forum
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10 years ago

What's the difference between an Avalon MM Master and an Avalon MM Slave

I need to design an Avalon MM IP component that allows software running on the HPS of a Cyclone V FPGA to access an external comms chip and an SRAM chip. The comms chip has a memory mapped register s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

A processor or DMA implements Avalon-MM Master interfaces.

A UART or GPIO peripheral implements Avalon-MM Slave interfaces.

A master generates bus requests, while a slave receives those requests.

You would want to implement an Avalon-MM Slave interface.

Also, look into the bundled Tri-State bridge component.