What's the burst length of SDRAM in Nios II?

You're welcome!

In your case, I don't know how DMA is going to help, because you want to read/write to SDRAM from the CPU. DMA will speed up the access when you have another memory area or device you want to transfer blocks of data from/to, without CPU intervention. The reason DMA works well with SDRAMs is because it generates low level bus requests, which will help keeping the SDRAM pipeline busy, hence the one word per clock cycle stream. You should be able to achieve something similar in software, as long as you dont have other processes/interrupts kicking in and disrupting the consecutive address requests.

You said that you have an incrementing pointer for reading the SDRAM, but where are you reading the data into? Is the destination address in the SDRAM as well? In this case, the bus accesses would be read/write/read/write, hence the bad performance - probably the SDRAM controller needs to open/close the row for each access. In this case, if the data block is big and you cannot use register variables, the solution I see is adding an extra on-chip RAM peripheral and instructing the compiler to use this area for your array.

Regards,

Clancy