Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThey can be connected to other vhdl blocks to force the nios cpu into a reset state (it keeps reading the first instruction from the reset vector, but decides not to execute it), and to find out whether the cpu is in reset (pulsed active for one clock - probably when the execution is aborted).
To be useful the 'reset taken' line needs latching and masking with 'reset request'.