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Thank you for your answer Bill.
Where do I find this cache configuration?
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I meant to be sure to use non-cached addresses with SGDMA. With the Altera TSE and Interniche you don't need to worry about this.
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I use a standard design provided with my dev board, with minor changes to fit my needs:
- Nios II/f core
- TSE MAC + sgdma rx/tx + on chip memory descriptor memory
- Micrium RTOS II + Interniche stack
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This could be different in NIOS II 9.x but in 8.x the National Semi DP83640 is not listed in the supported PHY table. Do you have an alt_tse_phy_profile entry for it, or can you confirm the entry being used is identical to the DP83640?
Just because this came to you as a kit and/or with drivers doesn't mean it's correct. Our development board (I think from the same company as yours) had a hardware design flaw, and the supplied TSE and PHY Altera drivers are NOT bug free.
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The only reference to cache I could find is in Nios configuration in sopc builder. Should I disable it?
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No. Performance will be shot doing so.
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Regarding your question about the driver, all mac and phy initialization is performed by OS and stack: that's why is said it was the standard one.
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Got it. Don't take that to mean it's bug-free. You could be doing something that is exposing a bug.
Bill
Honored Contributor
