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Sounds like a data cache problem. Be sure to use non-cached addresses with the TSE.
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Thank you for your answer Bill.
Where do I find this cache configuration?
I use a standard design provided with my dev board, with minor changes to fit my needs:
- Nios II/f core
- TSE MAC + sgdma rx/tx + on chip memory descriptor memory
- Micrium RTOS II + Interniche stack
The only reference to cache I could find is in Nios configuration in sopc builder. Should I disable it?
Regarding your question about the driver, all mac and phy initialization is performed by OS and stack: that's why is said it was the standard one.
Cris
Honored Contributor
