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How does it happen exactly? Is the rx_en signal suddenly de-asserted in the middle of a packet, or is it entirely de-asserted?
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When there's the problem rx_en is always low, it doesn't become de-asserted in the middle of packet.
I also checked the rxerr signal from phy but it signals nothing.
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Here are a few possible causes I could think of:
- bad connection between the phy and the FPGA, or noise/coupling on some signals
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I use a off-the-shelf development board (DBC3C40), so I exclude connection problems. Moreover the board has two ethernet ports and both show exactly the same behaviour.
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- the MAC and PHY are'nt using the same clock to communicate on the MII bus
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I tried several clock design: same clock for mac and phy, pll for clock regeneration, phase shifting them and so on, but so far I again obtained always the same behaviour.
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- bad configuration of the PHY (MDIO registers)
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I used the standard configuration provided with the driver. Can you suggest me anything I can change?
I read the phy datasheet but I couldn't find anything that can be related to my problem.
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- power supply problems on the PHY (bad filtering and/or decoupling)
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I'd exclude for the former reason. Should I trust the board supplier or not?
Regards.
Honored Contributor
