Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Weird Ethernet problem

Premise: I don't know if this weird problem is related to TSE, sgdma or Nios code. Please help me to identify, or better, to solve it. I'm using Nios II with tse mac and National Semi DP83640 p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't think that the problem comes from the Mac, the rx_en signal being generated by the PHY... How does it happen exactly? Is the rx_en signal suddenly de-asserted in the middle of a packet, or is it entirely de-asserted?

Here are a few possible causes I could think of:

- bad connection between the phy and the FPGA, or noise/coupling on some signals

- the MAC and PHY are'nt using the same clock to communicate on the MII bus

- bad configuration of the PHY (MDIO registers)

- power supply problems on the PHY (bad filtering and/or decoupling)