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Altera_Forum
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13 years ago

Weird Bug: Trivial component affects NIOS operability

Hi there, I have a really strange bug I can't figure out. I am developing some firmware for a proprietary testboard that utilizes the Cyclone FPGA. It contains 1 NIOS processor with multiple PIOS and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Usually this indicates a timing problem. A small change on the design makes the placement and route take a complete different road, and makes your design work, only by chance.

Is your design fully contrained and does it meet all timing requirements?