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- Altera_Forum
Honored Contributor
Hi,
Right click on that message > Locate in source design. It is a curious name :-) Regards.
when i compliling my top verilog design, then with warning [ Warning (12110): Net "_" is missing source, defaulting to GND], what is it? what statement cause it?
who can help me? thx!Hi,
Right click on that message > Locate in source design. It is a curious name :-) Regards.