Altera_ForumHonored Contributor15 years ago[Warning (12110): Net "_" is missing source] what is it? when i compliling my top verilog design, then with warning [ Warning (12110): Net "_" is missing source, defaulting to GND], what is it? what statement cause it? who can help me? thx!Show More
Altera_ForumHonored Contributor15 years agoHi, Right click on that message > Locate in source design. It is a curious name :-) Regards.
Recent DiscussionsAshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)Nios-V on Cyclone IVSolvedDebug Know-How: Ashling* RiscFree* NIOS® V debug using Command LineNIOS SDK SBOM/FOSS info