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Altera_Forum
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16 years ago

Vhdl question

I come on this pice of code: SIGNAL clockticks200k: INTEGER RANGE 0 TO max200k; What dose Range stand for?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You're welcome.

I should have also mentioned that a range constraint also guides the synthesis tool. The synthesis tool should only use as much resources as are necessary to represent the outer bounds of the integer range of the declared signal.