Honored ContributorVHDL_Help
I'm trying to write a quadruple 2-line to 1-line mux to 7segment display here is my code but I don't understadn the errors that the compilier is giving me I'm working in Quartus 2 V9.1.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux4to7segdisplay IS
PORT ( NUM1 :IN std_logic_vector (3 DOWNTO 0);
NUM2 :IN std_logic_vector (3 DOWNTO 0);
S :IN BIT;
--bcd :IN std_logic_vector (3 DOWNTO 0);
A :OUT BIT;
B :OUT BIT;
C :OUT BIT;
D :OUT BIT;
E :OUT BIT;
F :OUT BIT;
G :OUT BIT);
END mux4to7segdisplay;
ARCHITECTURE display OF mux4to7segdisplay IS
BEGIN
--PROCESS (S,NUM1,NUM2,bcd)
IF (S='0')Then
ELSIF(NUM1="0001")THEN
A<='0';
B<='1';
C<='1';
D<='0';
E<='0';
F<='0';
G<='0';
ELSIF(NUM1="0010")THEN
A<='1';
B<='1';
C<='0';
D<='1';
E<='1';
F<='0';
G<='1';
ELSIF (NUM1="0011") THEN
A<='1';
B<='1';
C<='1';
D<='1';
E<='0';
F<='0';
G<='1';
ELSIF (NUM1="0100") THEN
A<='0';
B<='1';
C<='1';
D<='0';
E<='0';
F<='1';
G<='1';
ELSIF (NUM1="0101") THEN
A<='1';
B<='0';
C<='1';
D<='1';
E<='0';
F<='1';
G<='1';
ELSIF (NUM1="0110") THEN
A<='0';
B<='0';
C<='1';
D<='1';
E<='1';
F<='1';
G<='1';
ELSIF(NUM1="0111")THEN
A<='1';
B<='1';
C<='1';
D<='0';
E<='0';
F<='0';
G<='0';
ELSIF(NUM1="1000")THEN
A<='1';
B<='1';
C<='1';
D<='1';
E<='1';
F<='1;
G<='1';
ELSIF (NUM1="1001") THEN
A <='1';
B<='1';
C<='1';
D<='0';
E<='0';
F<='1';
G<='1';
ELSE
A<='1';
B<='0';
C<='0';
D<='1';
E<='1';
F<='1';
G<='0';
END IF;
ELSE
IF (NUM2="0000")THEN
A<='1';
B<='1';
C<='1';
D<='1';
E<='1';
F<='1';
G<='0';
ELSIF (NUM2="0001")THEN
A<='0';
B<='1';
C<='1';
D<='0';
E<='0';
F<='0';
G<='0';
ELSIF (NUM2="0010") THEN
A<='1';
B<='1';
C<='0';
D<='1';
E<='1';
F<='0';
G<='1';
ELSIF (NUM2="0011") THEN
A<='1';
B<='1';
C<='1';
D<='1';
E<='0';
F<='0';
G<='1';
ELSIF (NUM2="0100") THEN
A<='0';
B<='1';
C<='1';
D<='0';
E<='0';
F<='1';
G<='1';
ELSIF (NUM2="0101") THEN
A<='1';
B<='0';
C<='1';
D<='1';
E<='0';
F<='1';
G<='1';
ELSIF (NUM2="0110") THEN
A<='0';
B<='0';
C<='1';
D<='1';
E<='1';
F<='1';
G<='1';
ELSIF (NUM2="0111") THEN
A<='1';
B<='1';
C<='1';
D<='0';
E<='0';
F<='0';
G<='0';
ELSIF (NUM2="1000") THEN
A<='1';
B<='1';
C<='1';
D<='1';
E<='1';
F<='1;
G<='1';
ELSIF (NUM2="1001") THEN
A<='1';
B<='1';
C<='1';
D<='0';
E<='0';
F<='1';
G<='1';
ELSE
A<='1';
B<='0';
C<='0';
D<='1';
E<='1';
F<='1';
G<='0';
END IF;
END IF;
END display;
Here are the errors:
Info: ************************************************** *****************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Nov 13 19:34:53 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux4to7segdisplay -c mux4to7segdisplay
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(25) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(25) near text "Then"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(26) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(34) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(34) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(42) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(42) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(50) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(50) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(58) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(58) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(66) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(66) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(74) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(74) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(82) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(82) near text "THEN"; expecting "<="
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(90) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at mux4to7segdisplay.vhd(90) near text "THEN"; expecting "<="
Info: Found 0 design units, including 0 entities, in source file mux4to7segdisplay.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
Error: Peak virtual memory: 227 megabytes
Error: Processing ended: Sat Nov 13 19:34:55 2010
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 21 errors, 0 warnings
Any help will be GREAT!!!!
Thank you
Heath
