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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL Generic map

Hi,

Generic map( duty => 5)

I got above code from one of the LPM and need to modify it in order to make the value of duty read from another module.

if I make it,

Generic map( duty => n) and varie the value of n in another module (n is a signal type) - it doesn't allow.

Is there any method of doing this?

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    it doesn't allow

    --- Quote End ---

    You're talking in riddles.

    Passing generic parameters down the hierarchy is everydays VHDL.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You must pass constants (or at least locally static values) through generic maps.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    well..that's not a helpful answer to a VHDL beginner :(

    "Duty" is defined as type NATURAL in the package.

    how can I pass the value from the top level entity? What type the "n" should be is my question. (n should vary its value at the top level entity - in a loop)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You may instantiate multiple different components with different values for "duty" in your top-level entity, but the value you pass to any one component must NOT vary. Inside what kind of loop are you instantiating this component?

    If this is not helpful, please state your problem more clearly and in further detail.