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Honored Contributor
Honored Contributorvery simple PLL usage issue
Hello, I'm working on a custom pcb with a cyclone V GX. I'm having issues getting an output from the altera megafunction PLL, it is unresponsive. My test design has a nios II which succe...
Altera_ForumHonored Contributor
Honored ContributorAre you generating phase shifted clock from PLL? If yes then provide phaseshift in ps instead of degree. I faced this issue with Altera PLL megafunction.
Are you using SDRAM as a program memory for NIOS? If yes then there is chance after inserting PLL,SDRAM clock routing is changed and due to that SDRAM is not working. To test the hello world you can use ONCHIP Memory.
