Honored Contributor
Honored ContributorThanks for taking the time Moose. You've cleared up things for me, I think. ;-)
If I understand right, it's all about fit, functionality and optimization. The NIOS is just one core implementation on the FPGA. I assume, one could implement just about any core, if the FPGA is big enough. Option 1 - Choose an off-the-shelf micro that has the features closest to the application. Write the code and you're done. Option 2 - Choose an OTS micro that has more than is needed, for future expansion. Option 3 - Choose an OTS micro and add specialized peripherals e.g. LTC 2400 24 bit A/D Option 4 - Pick an FPGA, and a core design, design needed peripherals with remaining gates then write code. Extra peripherals/ram/flash may be needed. An FPGA has the advantage of being almost 100% reconfigurable but there's an extra step to configure (and debug!) the on-chip peripherals. There may be some speed gains in implementing some functions in hardware, which would be software in an OTS device. From where I sit, the FPGA solution is not really an option for prototypes or low volume runs. Any device cost savings would be lost in development costs. If I buy an OTS micro dev board, I can buy a micro that is over the top, but then I'm coding right away. Once my design is set, I can downscale to a more appropriate device. I'm not saying this as gospel; it's just how I see things right now. If I'm missing something, I encourage you, or anyone else, to set me on the right path. Cheers, Bob
