This happens on the Nios II development boards because there is a pin that drives out of the FPGA to the CPLD on the board. This pin when pulled low tells the CPLD to reprogram the board (look at the full featured design for the reconfig_n pin). So if you don't use the pin and don't have unused I/O set to input tristate, after downloading the pin goes low and the CPLD re-downloads a new hardware image out of flash.
A side effect of this is if you flash program a design that causes this behavior you'll see the LEDs on your board flash on and off really fast (because you just created an never ending configuration loop). Not that I've ever done this .......
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