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Altera_Forum's avatar
Altera_Forum
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16 years ago

Verify problem while runing on Nios II hardware

Hi there,

when i try to run my project on the Nios II hardware i get the following problem:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Reading System ID at address 0x00070000: verified

Initializing CPU cache (if present)

OK

Downloading 00080000 ( 0%)

Downloaded 43KB in 0.7s (61.4KB/s)

Verifying 00080000 ( 0%)

Verify failed between address 0x80000 and 0x8ABDF

Leaving target processor paused

I use the SRAM memory on DE1 board which has the Cyclone II FPGA. I also checked the base and end address for SRAM, and there is also no overlaping. The SRAM memory has the base address 00080000 and 0008ffff end address. I also use the on-chip memory for better perfomance.

Have anyone an idea how to fix that problem?

Best regards!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Please check the Vector and Exception address are Pointing to?

    Which QII verison are you using.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    This problem may arise due to wrong pin assignment of an SRAM, so just check the pin assignment if any mistake is there.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Check for proper pin assignment of -

    1. Clock

    2. Reset

    Also check in 'system library properties' that you are using on chip memory, and not sram, as program memory
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It's happened to me once or twice because I forgot to use bidir pins for the data lines.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks to all for your suggestions! I checked the pin assignment and it's perfect,there aren't problems. Also, the sys_lib is OK, I choose the SRAM memory as place for my code. The clock signal has the appropriate pin.

    I fixed the problem, it was my mistake because I set the data bus as only output direction and now I use it as bidirectional direction and it works. Sometimes we have to look for the simpliest causes :rolleyes:. Before i fixed the problem I tried many options. Jakobjones gave me very good suggestions.

    Again, thanks to all, Lightline you was right and if I wouldn't fix it before your

    suggestion were good!

    Best regards!