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Altera_Forum
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21 years ago

Using the 3.3V Proto-Card Pins On Nios Board

hi, I'm using the @ltera Nios Developement Board, with the Apex20K200E FPGA onboard, for SoC design implementations. Can anyone confirm that for the 3.3V proto-card pins to be used a...
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Altera_Forum
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21 years ago

Hey;

You are correct, for the Proto - card connectors JP11 JP12 and JP13 you need to tie pin_V6 low in order to enable the quick switches that the IO connections pass through to the headers. The proto - card connectors JP8 JP9 and JP10 do not require this because they do not have quick switches in between them and the PLD. These Apex boards are the only ones that require that pin to be pulled low. All the boards since then have the quick switches on all the proto - card connectors but they are always active and do not require an enable signal.

Kenyon