Using IDT71V416 as 16-bit RAM

I added the ram as user logic

(remark one userlogic for both ram chips,

this is necessary to get one block of memory for system library properties)

PORTNAME WIDTH DIRECTION SHARED TYPE

address 19 input yes address

write_n 1 input yes write_n

read_n 1 input yes read_n

data 16 inout yes data

chipselect_n 1 input --- chipselect_n

be_n 2 input yes byteenable_n

I added external logic (one not and two ors's) to generate the

two different CS signals

SRAM_CS0_N = SRAM_CS or A19

SRAM_CS1_N = SRAM_CS or (not A19)

if you want to use only one ram chip, then reduce address to 18 and remove

external logic.

Dave,

The reasoning is that we cannot possibly test every permutation of RAM available. Instead the we provided pre-fabbed support for the devices on our development boards, and then the I/F to user logic (now Component Editor) to add a custom interface that has the exact width/depth/timing settings that you need.

Fischer & Jesse,

Thank you both for your help. I'll try out the user logic route.