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Altera_Forum's avatar
Altera_Forum
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9 years ago

User space application access to Hardware. HPS FPGA bridge

Dear all

I am a newbie on Altera SoC architecture, so I am trying to run a simple C Userspace application on an Arria 10 SoC (attached file custom_software.zip).

The application tries to access a gpio controller (offset adress 0x0000_1000) controller via the hps_i_bridge_lw using a mmap function.

When running using sudo, i got the following error message :

root@linaro-nano:~/sandbox# sudo ./FPGAHPS

[ 1749.499651] Unhandled fault: external abort on non-linefetch (0x818) at 0x760

[ 1749.507198] pgd = ecccc000

[ 1749.509891] [76c30000] *pgd=6df89831, *pte=ff201743, *ppte=ff201c33

The h2f_lw_axi_master seems to be present in the kernel and uboot devicetree.

Also i tried to access the address 0xFF200000 (h2f_lw_axi_master) in the U-boot environment using md/mw commands and it makes U-boot to restart.

http://www.alteraforum.com/forum/attachment.php?attachmentid=12403&stc=1

I must have done something wrong, any ideas ?

Thanks in advance

Mathieu

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    did you release the bridge from reset, after programming the image to the FPGA?

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi

    On our board, the FPGA is loaded at startup from a flash memory using Active Serial. The resets signal from fpga to hps are hps_f2h_cold_reset_req_reset_n, hps_f2h_warm_reset_req_reset_n, they start at 0 and go high after few clock cycle.

    However I haven't seen any signals named lwhps2fpga_bridge_rst_n, which I think is responsible of the lw bridge reset.

    I found some hint there : https://lists.rocketboards.org/pipermail/rfi/2015-august/003260.html

    I have modified the command for enabling specifically the lw_hps-2-fpga bridge but i got the following errors, i think the address is still protected

    In: serial

    Out: serial

    Err: serial

    Model: SOCFPGA Arria10 Dev Kit

    Net: dwmac.ff802000

    Hit any key to stop autoboot: 0

    SOCFPGA_ARRIA10# mw.l 0xffd13500 0x1

    SOCFPGA_ARRIA10# mw.l 0xffd13504 0x1

    SOCFPGA_ARRIA10# mw.l 0xffd11004 0xffffffff

    SOCFPGA_ARRIA10# md.l 0xffd0502c 1

    ffd0502c: 0000003f ?...

    SOCFPGA_ARRIA10# mw.l 0xffd0502c 0x3d

    SOCFPGA_ARRIA10# md.l 0xffd0502c 1

    ffd0502c: 0000003d =...

    SOCFPGA_ARRIA10# md.l 0xff200000 1

    ff200000:data abort

    pc : [<ffe0ecae>] lr : [<ffe0ec8f>]

    sp : ffe3be28 ip : ff200000 fp : 00000000

    r10: ff200000 r9 : ffe2e310 r8 : ff200000

    r7 : 00000001 r6 : 00000004 r5 : 00000004 r4 : 00000001

    r3 : ffe0d255 r2 : 00000001 r1 : ffe3be3c r0 : 00000009

    Flags: nZCv IRQs on FIQs off Mode SVC_32

    Resetting CPU ...

    resetting ...

    Any hint ?

    Thanks for your help

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Dear all

    I think I have found a begging of a workaround.

    If you encounter a similar problem like me, here is the process :

    - first of all enable also the standard HPS-2-FPGA bridge in your Qsys system

    - follow the same instruction here https://lists.rocketboards.org/piper...st/003260.html

    then it is possible to access the FPGA bridge from U-boot

    I am able to run a bare metal application and access the registers.

    But still not able to do a mmap in Linux userspace (of course with the administrator's rights)

    Regards

    Mathieu