User space application access to Hardware. HPS FPGA bridge

Hi

On our board, the FPGA is loaded at startup from a flash memory using Active Serial. The resets signal from fpga to hps are hps_f2h_cold_reset_req_reset_n, hps_f2h_warm_reset_req_reset_n, they start at 0 and go high after few clock cycle.

However I haven't seen any signals named lwhps2fpga_bridge_rst_n, which I think is responsible of the lw bridge reset.

I found some hint there : https://lists.rocketboards.org/pipermail/rfi/2015-august/003260.html

I have modified the command for enabling specifically the lw_hps-2-fpga bridge but i got the following errors, i think the address is still protected

In: serial

Out: serial

Err: serial

Model: SOCFPGA Arria10 Dev Kit

Net: dwmac.ff802000

Hit any key to stop autoboot: 0

SOCFPGA_ARRIA10# mw.l 0xffd13500 0x1

SOCFPGA_ARRIA10# mw.l 0xffd13504 0x1

SOCFPGA_ARRIA10# mw.l 0xffd11004 0xffffffff

SOCFPGA_ARRIA10# md.l 0xffd0502c 1

ffd0502c: 0000003f ?...

SOCFPGA_ARRIA10# mw.l 0xffd0502c 0x3d

SOCFPGA_ARRIA10# md.l 0xffd0502c 1

ffd0502c: 0000003d =...

SOCFPGA_ARRIA10# md.l 0xff200000 1

ff200000:data abort

pc : [<ffe0ecae>] lr : [<ffe0ec8f>]

sp : ffe3be28 ip : ff200000 fp : 00000000

r10: ff200000 r9 : ffe2e310 r8 : ff200000

r7 : 00000001 r6 : 00000004 r5 : 00000004 r4 : 00000001

r3 : ffe0d255 r2 : 00000001 r1 : ffe3be3c r0 : 00000009

Flags: nZCv IRQs on FIQs off Mode SVC_32

Resetting CPU ...

resetting ...

Any hint ?

Thanks for your help

Regards