Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Unused pins from FPGA to LAN91C111 (through NIOS)

Hi all,

I am interfacing LAN91C111 chip with NIOS II processor in an Altera

Stratix device.

After I finish generating my system in SOPC Builder, I create the bdf

file (or an hdl file) of the system in order to examine the INs and

OUTs of the system. I observed that for lan91c111, the only outputs

generated were IO RD and WR, ADS, WEN, BE, IRQ, Reset etc.

I checked the schematic of the NIOS Development Board (1S10ES), where

there are many more signals going to lan91c111 chip from the FPGA (eg.

CYCLE, LCLK etc.). However my NIOS design doesn't generate all the

signals of the lan91c111 inputs. From where do I get these signals?

I noticed that whichever signal port was not generated in the bdf,

should be high for asynchronous operation of the Ethernet. This is the

case with NIOS development kit as well, in my opinion. Are these

signals tristated from FPGA. In that case, can I do the same outside

the FPGA chip using some high resistance (and hence save some of the

FPGA pins) since I may never use sync mode of operation in my design.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hello,

    The circuit to/from the lan91c111 was designed with maximum flexibility in mind; the chip can be used in a variety of data bus widths in both sync. and async modes. On the Stratix dev boards, we use 32-bit async. mode; the SOPC Builder component only exports signals necessary for operation in this mode.

    Thus, there are leftover signals that have to be pulled high/low for 32-bit async operation to work; I would reccomend careful study of both the Nios dev board schematic (on the 91c111 page) as it will show that many of these signals, while tied to the FPGA, have pullup/down resistors to get the chip into 32-bit async. mode when the FPGA is not driving the signals. In addition, you'll find a couple of ethernet signals tied in the Nios HW example designs (standard, full_featued, etc.). These two pieces of reference material should explain how the interface is constructed.