Unused pins from FPGA to LAN91C111 (through NIOS)

Hello,

The circuit to/from the lan91c111 was designed with maximum flexibility in mind; the chip can be used in a variety of data bus widths in both sync. and async modes. On the Stratix dev boards, we use 32-bit async. mode; the SOPC Builder component only exports signals necessary for operation in this mode.

Thus, there are leftover signals that have to be pulled high/low for 32-bit async operation to work; I would reccomend careful study of both the Nios dev board schematic (on the 91c111 page) as it will show that many of these signals, while tied to the FPGA, have pullup/down resistors to get the chip into 32-bit async. mode when the FPGA is not driving the signals. In addition, you'll find a couple of ethernet signals tied in the Nios HW example designs (standard, full_featued, etc.). These two pieces of reference material should explain how the interface is constructed.