Unloading Packet

Using a PIO is the easiest solution, but you need some synchronisation signals in addition to the data signals, to tell to your VHDL component when new data is available, and maybe for your VHDL component to tell to the CPU when it is ready to receive more data.

OR as an alternative, you can use a DMA. Your VHDL component will just need to have an Avalon Stream Sink interface to receive the data, and you can connect it to a memory-to-stream SGDMA in SOPC Builder / QSys.