Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

unexpected input at Nios core!

Hi all, I have got an unexpected input at my NIos core, and I dont know what its functionality. it is an: E_en_to_the_cpu_0 input. Can anybody tell me something about this? thanx
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

I thought this sounded familiar.

This bug slipped into version 1.01 of the JTAG Debug Module. It only shows up when using the debug module with the Nios II/e core.

It's fixed in version 1.1, and the workaround for version 1.01 is to connect the signal to logical 1 or VCC.