Understanding Altera Mailbox Core

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I&#39;ve got quite a problem in understanding how the Altera Avalon Mailbox Core really works.[/b]

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They are basically two mutexes...

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1.

How is the shared mailbox memory reserved?

In addition to using dedicated memory (e.g. on-chip-memory) as mailbox memory,

it is possible to use main memory (in my case sdram) for communication.

The exact location of the part used by the mailbox is specified by an offset and size.

In that case, how is it accomplished, that this part of memory is exclusively used

as a shared memory for mailbox communication? How does the linker know not

to use this part of (main) memory? I&#39;ve looked into many files (like generated.x)

and could not find any kind of memory reservation.[/b]

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As long as I remember, there has been no memory reservation for the mailboxes. you have to supply them by hand.

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2.

How does cache bypass work when accessing shared mailbox memory?

While access to the registers of the mailbox core device uses the "io" instructions

for bypassing the data cache, the read and write instructions the HAL implementation

uses to access the shared memory are the normal ones. It all boils down to a

&#39;stw&#39; and a &#39;ldw&#39; instruction. They also don&#39;t use the "bit32-bypass", as the address

is the normal one (not &#39;or&#39;-ed with 0x80000000). So how does the write-back of data

to the shared memory work in this case?[/b]

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hmmm... I think it simply does not work... probably the only way to get data cache bypassing is to pass an addres at initialization which already has the bit31 enabled.

Btw, we internally do not use Altera Mailboxes, because they tend to fix the communication paradigm in the hardware instead making it flexible... Instead, we prefer in general to used OS shared resources to get mutual exclusion between the various CPUs. For example, you can look at the fifo demo in the evidence literature page (http://www.evidence.eu.com/content/view/71/104/)...

bye

PJ