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Altera_Forum
Honored Contributor
Honored Contributoruncontrolled SDRAM content change
Hi, I use a code which checks external SDRAM () by writing 0xAAAA and 0x5555 patterns. But the code always return an error code! When I check step by step SDRAM content with NIOSII IDE I can ...
Altera_ForumHonored Contributor
Honored ContributorYes I'm sure SDRAM settings are correct and constraint are also given for Quartus and no error/warning is present after compilation.
External frequency is 50MHz and internal (PLL outputs) are 80MHz But now I remember I use the NiosII/e CPU. So it can't be a cache issue because this version of CPU doesn't manage cache at all! I continue to investigate. If somebody has any other idea... you are welcome :confused:
