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Altera_Forum's avatar
Altera_Forum
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8 years ago

unable to build a program in NIOS II IDE

Hello everyone,

I am facing a problem with building a project on NIOS II IDE. I have done a simple program and when i build the project, it shows the following message

"make -s all includes make: *** No rule to make target `C:/Users/H_AB/Desktop/Doc/Nouveau', needed by `/cygdrive/c/Users/H_AB/Desktop/Doc/Nouveau/Debug/system_description/../obj/generated_app.mk-t'. Stop."

I can't identify the error and i dont know how to deal with this. Any ideas please ?

Thank you.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hello Berkoka,

    Since you are new to the forum, I ask some possibly too basic questions/hints;

    There are a numer of Nios tutorials that are very basic. (My first nios tutorial.)

    You might try to get these to work and then see where the differences are with your project.

    Can you explain what the different project steps are you did?

    Which hardware ar you using ?

    You might want to leave a backup on this site of your project ? (quartus / project / archive project)

    Best regards,

    Johi.
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Johi,

    Thank you for your reply. Yes, even i followed the steps used in a tutorial (First nios tutorial) the error message persists.

    Today, i tried to save the quartus and the nios project in the folder where the quartus software is installed and it works, the nios project is built successfully.

    However, when i ran the project, another error message is shown and idont know why

    """ "Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Pausing target processor: not responding.

    Resetting and trying again: FAILED

    Leaving target processor paused" """

    The hardware is: Altera Cyclone III EP3C40F780C8N.

    Thank you iin advance
  • Altera_Forum's avatar
    Altera_Forum
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    Hello Berkoka,

    Getting nios up and running can be a real challenge.

    You do a number of steps in qsys, generate a vhdl / verilog application compile it and download it.

    And then, hope that it works ...

    If not it can be really difficult to try.

    You can have a lot of different causes of problems that make it go wrong so some ideas:

    => Were you able to build a simple application verilog / vhdl that makes a led blink with your board in quartus?

    (=> Just to make sure board, communcations, clocks work ? (Test))

    => In qsys, make an application with only onchip ram, no SDRAM, SDRAM and SRAM are possible cause of problems. Just the basics.

    (=> In line with tutorial normally.)

    => In eclipse, generate application based on hello world small. (based on .sopc) hello world can be too large for some fpga's.

    => If you start the application in eclispse, click right on the project, and then use debug as Nios II hardware.

    => Sometimes you can have a problem with timestamp or id, you can check ignore mismatsched timestamp and id if you go to application, right click, debug applications, tab 2.

    Good Luck,

    Johi.
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Anand Raj Shankar, Johi

    First of all, thank you for your help.

    It is Quartus 9.1 that im using. But with the latest version (quartus 13) i will need even the latest version of Nios II IDE.

    => Yes, i did just a simple application "bliking a led" with vhdl and it works on the board.

    => Since i'm a beginner in Nios, i did a simple application " LED lights flashing" given by the developpement Manual NIOS II. So i followed all the steps mentioned on the manual.

    => Yes, i did it with only onchip RAM.

    => I tried with debug as Nios II hardware, the problem persists.

    Thank you. Regards
  • Altera_Forum's avatar
    Altera_Forum
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    Hello,

    I tried with the latest version as you suggested and it works!

    Thank you. Regards,