Hi again, sorry I haven't replied, I didn't get an email about your responses (even though I am subscribed to this thread) :/
I have found a solution to one of the problems (the data being read incorrectly from the SRAM on the ethernet controller). I have replaced the verilog interface that simply wires up the avalon slave to the ethernet controller with a simple state machine to ensure the timing constraints described in the datasheet are adhered to. With this fix, the driver no longer gets out of sync with the controller after a while, and everything is considerably more stable (I left my PC pinging the board overnight -- 20,000 responses, 0 lost)
However, there is still a problem when there is a fair bit of traffic to/from the board. I think I have identified the cause (a bug in the output routine of the driver). I will fix this bug and post the changes I have made once I verify that everything is working...