Forum Discussion
Honored ContributoruClinux MMC SPI Driver
Just to let everyone know, an MMC SPI Driver for Alteras SPI Core (modified) is in the works.. currently, cards can be recognized, read/write, and even partitioned.. but some bugs are being worked out. If anyone is interested in an early release, let me know....
56 Replies
Altera_Forum--- Quote Start --- originally posted by hippo@Apr 4 2006, 07:49 PM i am working on it , right now. still cleaning from 2.6.11 to 2.6.12 .<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14030)
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--- Quote End --- cool - you can post a diff patch for each stage you go and I'll quickly test it out for you on my hardware. It would be nice if kernel.org had a SVN repo; then I could at least tell when the MMC layer changed!
- Altera_Forum
Sure , I will send you the results for early testing.
<div class='quotetop'>QUOTE </div> --- Quote Start --- It would be nice if kernel.org had a SVN repo; then I could at least tell when the MMC layer changed![/b] --- Quote End --- The kernel.org use "git" for version control. But I didn't try it yet. - Altera_Forum
J,
I am still working on 2.6.12 . I am checking them again other arch, to find out the problem in nios2 kernel. Will let you know when I have some found. - Altera_Forum
It is strange.
when I set ddr sdram size from 64M to 8M, the page allocation failure did not happen. is it hardware issue? I will focus on this problem, and will not be available for others. sorry. - Altera_Forum--- Quote Start --- originally posted by hippo@Apr 5 2006, 09:21 PM it is strange.
when i set ddr sdram size from 64m to 8m, the page allocation failure did not happen.
is it hardware issue?
i will focus on this problem, and will not be available for others. sorry.
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14082)
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--- Quote End --- Hey hippo,l I'm using a 32M DDR chip; that's really weird though. So you think it's a problem with the DDR core itself, maybel ocking up the avalon bus? <div class='quotetop'>QUOTE </div> --- Quote Start --- I will focus on this problem, and will not be available for others. sorry.[/b] --- Quote End --- I'm sorry, what do you mean by this?
- Altera_Forum
I am using ddr sdram of 64M chip (x16) . I changed the ddr size to 8M in ptf for hwselect, and did not change the sof. I will do more testing on this, eg 16M 32M.
Please try out on yours. I mean, I will not have time to help others. I have to resolve this issue first. - Altera_Forum
ok, i understand; I will try this out to confirm, and I will have more time tomorrow to investigate. I will get bak to you shortly though.
- Altera_Forum
16M is OK.
I just found there is ddr core update 3.3.1 . I got qii and nios2 v6.0 beta , too. I will try out right now. - Altera_Forum
I am already using 3.3.1 (it's been out for some time) - QII 5.1 sp2 and NII 5.1 sp1
- Altera_Forum
Do you have boards that use sdram instead of ddr?
