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Altera_Forum's avatar
Altera_Forum
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15 years ago

UART loses bytes

Hi

I have a problem with the uart:

I can send single bytes from PC to FPGA and loop them back with out problem at baud rates up to 3MBd. But as soon as I write more than one byte at once or more bytes one after the other without delay, the FPGA loses some bytes. It gets worse with higher baud rates, but happens already at 9600Bd.

my setup:

- Cyclon II

- Nios II

- I use HAL to access the UART

some suggestions would be great

Thanks

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm using non blocking I/O on the FPGA. Blocking on the read because I'm polling for new data. Could this be the problem?

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    Altera_Forum
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    15 years ago

    Non-blocking implies that the send data are buffered and handled by an interrupt routine. You should check if everything is set up correctly.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks, I'll check this out. But does this have an influence on the receive?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi

    Unfortunately if I switch to blocking the same thing happens. I tried the communication in one direction from PC to NIOS. At 3MBd I always receive the last of 8Bytes on NIOS side. With smaller Bd rates more Bytes are received.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You should determine, if the data is possibly send out correctly and gets lost at the PC side. An oscilloscope or SignalTap are suitable tools.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    How can you connect the PC to the Cyclone?

    I have Cyclone III starter board, the only available pins are the JTAG, the boundary scan pins.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks fro your response. I understand that many uses that during design, but if I want to move my design to be final and get to an actual hardware, would I be still able to wire those JTAG and use them? In my design in real device there is not much data to be transferred to the FPGA, just few and no need for speed to do that.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    For a final design you can use a real RS232 line. You can still use the JTAG UART during development and switch once you have your hardware, the software isn't difficult to change.