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Altera_Forum
Honored Contributor
21 years agoUART ISR
Has Anyone implemented ISRs with AVALON UART? I'm trying to implement an ISR using the RRDY Interrupt bit in the STATUS register but it seems not work... has anyone an idea? i past a...
Altera_Forum
Honored Contributor
21 years ago --- Quote Start --- originally posted by rugbybloke@Sep 2 2005, 10:02 AM if you look in the directory altera\kits\nios2\components\altera_avalon_uart there is a driver for the uart, both interrupt driven and non-interrupt driven. i suspect that your problem is that the uart driver is automatically installed on your system, so it is handling the isr. you will be able to tell by looking in alt_sys_init.c, but you should probably read chapter 4 and 5 of the nios ii software developers handook to understand what alt_sys_init.c is first. --- Quote End --- I have looked into the codes you say, but i want to use as less as possible nios II API because I want to understand what I'm doing so I've registered by hand the IRQ associated to the IRQ mapped to the UART in the Hardware Platform. As I can read on datasheet i can see that " The UART core outputs a single IRQ signal to the Avalon interface, which can connect to any master peripheral in the system, such as a Nios II processor. The master peripheral must read the status register to determine the cause of the interrupt. Every interrupt condition has an associated bit in the status register and an interrupt-enable bit in the control register. When any of the interrupt conditions occur, the associated status bit is set to 1 and remains set until it is explicitly acknowledged. The IRQ output is asserted when any of the status bits are set while the corresponding interruptenable bit is 1. A master peripheral can acknowledge the IRQ by clearing the status register. At reset, all interrupt-enable bits are set to 0; therefore, the core cannot assert an IRQ until a master peripheral sets one or more of the interruptenable bits to 1. All possible interrupt conditions are listed with their associated status and control (interrupt-enable) bits in Table 6–5 on page 6–16 and Table 6–6 on page 6–18. Details of each interrupt condition are provided in the status bit descriptions. " so the IRQ should be setted automatically by the CPU and the only think I have to do is to register the irq to a custom IRQ handler function. There is an example on the datasheet for the PIOs Peripheral. I've looked into my alt_sys_init.c and I've found these: void alt_sys_init( void ) { ALTERA_AVALON_TIMER_INIT( TIMER, timer ); ALTERA_AVALON_JTAG_UART_INIT( JTAG_UART_0, jtag_uart_0 ); ALTERA_AVALON_SYSID_INIT( SYSID, sysid ); ALTERA_AVALON_CFI_FLASH_INIT( EXT_FLASH, ext_flash ); ALTERA_AVALON_LAN91C111_INIT( LAN91C111, lan91c111 ); ALTERA_AVALON_LCD_16207_INIT( LCD, lcd ); ALTERA_AVALON_UART_INIT( SERIALE_INT, seriale_int ); ALTERA_AVALON_UART_INIT( SERIALE_EXT, seriale_ext ); ALTERA_AVALON_UART_INIT( SERIALE_FUT, seriale_fut ); } yes I've 3 UARTS.... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif .... now if I recall the API, (but I wish that there is another method) how I have to do ??? there is any kind of example? shadowice