Forum Discussion
Honored ContributorTSE_MAC and memory
Hi Guys,
I've been building on examples and built a functioning ethernet. I can use the Nios for TCP TX/RX and i have interfaced some HDL for direct UDP TX. I'm currently developing on a DE2-115 and i'm merging this and the D5M camera example. I'll be building my own board soon. Problem is both use the SDRAM in their isolation and i need to merge. de2-115 has - sdram 2x64mb(16bit wide) used together as 32bit wide. - sram - 2mb 1. how can i determine how much memory the tse_mac needs? 2. does the niche stack use the sram? regarding point 1: the example i took just used the full 128mb and the BSP says it uses it all, but i imagine that more means it allocates it all. [update] point 2: I've tried to remove the SRAM in the past but my ethernet initialisation gets stuck after
INFO : TSE MAC 0 found at address 0x0c042000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group
INFO : PHY - Automatically mapped to tse_mac_device
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
INFO : PHY - Auto-Negotiation PASSED28 Replies
Altera_ForumPost the QSYS window screenshot.
Post the linker script configuration window screenshot. Where do You place the Nios startup vectors? What's the clock frequency of Nios system? Did You try to disable DHCP?- Altera_Forum
post the qsys window screenshot.
Attached is a zip containing the 4 images. (needed to zip because you can only upload 5 files per post) post the linker script configuration window screenshot. See attached BSP - Linkerscript where do you place the nios startup vectors? See attached Nios Start Up vectors what's the clock frequency of nios system? The Nios is running at 100Mhz and the TSE_MAC is at 50Mhz. All with applicable clock crossing bridges and FIFOS. did you try to disable dhcp? No yet, i will do so tonight. At work and i left my board at home. Again i really appreciate you effort to help and hope i can repay some time. - Altera_Forum
The problem is multi-clock design and bad constrains. I am pretty sure, that running JTAG-UART on 100MHz is too fast. I've failed running JTAG UART using such speed. Connect peripherals like jtag_uart, sysid, timer, etc through pipeline bridge. Also avoid multi-clock design as much as possible or try to check the data flow carefully.
E.g. I am running the whole system 85MHz, which runs without pipeline bridge, but I had problems running 100MHz Nios system, where issues where almost the same as Yours. JTAG printed only some of the lines and stopped. - Altera_Forum
That is sound advice thanks.
But it works until i remove the SRAM, which is what i find puzzling. - Altera_Forum
Well yes, but still, I've found many problems trying to build very fast, multi-clock Nios system. It requires to be strictly time constrained, without any errors/warnings.
- Altera_Forum
Turning off the DHCP worked. Why would this be so?
- Altera_Forum
Could be DHCP server or InterNiche problems. Who is DHCP provider? Windows server or other machine?
- Altera_Forum
The router they are plugged into. It'll be interniche somehow.
- Altera_Forum
I've heard some issues when InterNiche stack did not manage to understand DHCP messages sent by Windows Server.
You can try LwIP then. I've successfully managed to run the newest version of LwIP on TSE MAC. - Altera_Forum
I disabled DHCP and all started correctly, but i couldn't successfully telnet to it. So i'm a little concerned there. Perhaps i just need to step through and ensure i didn't disable something i shouldn't have.
This is concerning, time is a factor for me, i may not be able to switch stacks. I'm putting this on the back burner atm so i can sort hardware. I'm giving my self a week to have some schematics done. I'm actually trying to quickly design my own board (using BGA mounted). Instead of my marvell on my DE2, i need to use a SMSC lan 91c111. So hopefully its not too hard to get the HDL code for that particular chip. Hey to avoid the earlier problem perhaps the new chip will be better off
