The problem is multi-clock design and bad constrains. I am pretty sure, that running JTAG-UART on 100MHz is too fast. I've failed running JTAG UART using such speed. Connect peripherals like jtag_uart, sysid, timer, etc through pipeline bridge. Also avoid multi-clock design as much as possible or try to check the data flow carefully.
E.g. I am running the whole system 85MHz, which runs without pipeline bridge, but I had problems running 100MHz Nios system, where issues where almost the same as Yours. JTAG printed only some of the lines and stopped.